Mainline:Broadcom Kona/BCM590xx/Interrupts

The BCM590xx PMIC exposes a series of interrupts. This page describes the operation of these interrupts.

Interrupt overview

The BCM59054 has 128 IRQs; the BCM59056 has 64 IRQs. On both chips, interrupt handling is the same.

There are a total of 16 8-bit IRQ registers (16 INTx registers followed by 16 INTxMSK registers, allowing for a theoretical total of 128 IRQs.

Interrupt masking

Interrupts can be masked/unmasked by writing the relevant bit to INTxMSK registers. A value of 1 indicates that the interrupt is masked; a value of 0 indicates that the interrupt is unmasked.

Checking the status of an interrupt

Interrupts report their status in INTx registers; a bit of 0 indicates that the interrupt is not on, and a bit of 1 indicates that the interrupt is on.

When an interrupt is fired, the IRQ connected to the PMU is raised; this is an indication to the driver that an interrupt needs to be handled. Reading the value of the interrupt register clears the interrupt; once all interrupts are handled, the IRQ line goes down.

List of interrupts

TODO. See enum bcmpmu59xxx_irq in include/linux/mfd/bcmpmu59xxx.h in downstream for BCM59054 interrupts, enum bcmpmu_irq in include/linux/mfd/bcmpmu_56.h for BCM59056 interrupts.

Interrupt overview

Interrupt masking

Checking the status of an interrupt

List of interrupts

See also