Mainline:Broadcom Kona/BCM590xx/Interrupts: Difference between revisions

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The BCM59054 has '''128 IRQs'''; the BCM59056 has '''64 IRQs'''. On both chips, interrupt handling is the same.

There are a total of 16 8-bit IRQ registers (16 <code>INTx</code> registers followed by 16 <code>INTxMSK</code> registers, allowing for a theoretical total of 128 IRQs.

=== Interrupt masking ===

Interrupts can be masked/unmasked by writing the relevant bit to <code>INTxMSK</code> registers. A value of <code>0</code> indicates that the interrupt is masked; a value of <code>1</code> indicates that the interrupt is unmasked.

Interrupts can be masked/unmasked by writing the relevant bit to <code>INTxMSK</code> registers. A value of <code>1</code> indicates that the interrupt is masked; a value of <code>0</code> indicates that the interrupt is unmasked.

=== Checking the status of an interrupt ===

Interrupts report their status in <code>INTx</code> registers.

Interrupts report their status in <code>INTx</code> registers; a bit of <code>0</code> indicates that the interrupt is not on, and a bit of <code>1</code> indicates that the interrupt is on.

When an interrupt is fired, the IRQ connected to the PMU is raised; this is an indication to the driver that an interrupt needs to be handled. Reading the value of the interrupt register clears the interrupt; once all interrupts are handled, the IRQ line goes down.

== List of interrupts ==

@@ Line 4: / Line 4: @@
 The BCM59054 has '''128 IRQs'''; the BCM59056 has '''64 IRQs'''. On both chips, interrupt handling is the same.
+There are a total of 16 8-bit IRQ registers (16 <code>INTx</code> registers followed by 16 <code>INTxMSK</code> registers, allowing for a theoretical total of 128 IRQs.
 === Interrupt masking ===
-Interrupts can be masked/unmasked by writing the relevant bit to <code>INTxMSK</code> registers. A value of <code>0</code> indicates that the interrupt is masked; a value of <code>1</code> indicates that the interrupt is unmasked.
+Interrupts can be masked/unmasked by writing the relevant bit to <code>INTxMSK</code> registers. A value of <code>1</code> indicates that the interrupt is masked; a value of <code>0</code> indicates that the interrupt is unmasked.
 === Checking the status of an interrupt ===
-Interrupts report their status in <code>INTx</code> registers.
+Interrupts report their status in <code>INTx</code> registers; a bit of <code>0</code> indicates that the interrupt is not on, and a bit of <code>1</code> indicates that the interrupt is on.
+When an interrupt is fired, the IRQ connected to the PMU is raised; this is an indication to the driver that an interrupt needs to be handled. Reading the value of the interrupt register clears the interrupt; once all interrupts are handled, the IRQ line goes down.
 == List of interrupts ==