Mainline:Broadcom Kona/BCM590xx/ADC

Downstream driver: drivers/hwmon/bcmpmu59xxx-hwmon.c, drivers/misc/bcm59055-adc.c (for BCM59055 but very well commented, and seems to be about the same as other models).

The BCM590xx PMUs provide a 10-bit SAR (Successive Approximation) ADC.

Reading the ADC data

Each ADC channel has two registers which immediately succeed each other. These registers follow the layout outlined below.

To read the ADC data, one needs to combine the DATA_MSB bits (upper 2 bits, first two bits of the first register) with the DATA_LSB (lower 8 bits, entire value of the second register). An additional value at bit 2 is available to check the validity of the read data.

data = ((reg1 & 0x3) << 8) | reg2;

ADCCTRLx

Name	Bit	Description
Reserved/unknown	7:3	Reserved/unknown
READ_INVALID	2	If 1, the read is invalid; 0 otherwise.
DATA_MSB	1:0	Upper (most significant) 2 bits of the ADC data.

ADCCTRLx+1

Name	Bit	Description
DATA_LSB	7:0	Lower (least significant) 8 bits of the ADC data.

RTM (Real-Time Measurment)

The last ADC channel, RTM, is reserved for RTM (Real-Time Measurment) mode.

The process for performing an RTM read is as follows:

• In ADCCTRL1: (these can all be performed in one write)
  • Set the the RTM_CONVERSION bit to enable RTM mode
  • Write the channel number to read to the RTM_CHANN offset
  • Write the RTM_START bit to start the RTM read
• Wait for the ADC_RTM_DATA_READY interrupt.
• Perform a standard data read from the RTM ADC channel registers (see #Reading the ADC data).
• Clear the RTM_CONVERSION bit to disable RTM mode.

Register layout

Values given here are for the BCM59054. These registers are located on map 1.

ADCCTRL1 (0x20)

Contains settings for RTM mode.

Name	Bit	Description
RTM_CHANN	7:4	Channel to read in RTM mode.
RTM_CONVERSION	3	Enable (0) or disable (1) RTM mode. Prerequisite for performing an RTM read.
RTM_START	2	When set to 1, starts the RTM reading.
RTM_MAX_RST_CNT	1:0	Max reset count for RTM mode. Valid values are: 0 (0b00) - 1 1 (0b01) - 3 2 (0b10) - 5 3 (0b11) - 7

ADCCTRL2 (0x21)

Note	These are taken from the BCM59055 driver, and haven't been tested on the BCM59054 yet. Still, given that the ADCCTRL1 layout is the same, I suspect this one should be the same as well...

Name	Bit	Description
Reserved/unknown	7:6	Reserved/unknown
GSM_DEBOUNCE	5	If set to 1, enables ADC burst mode (todo, how does it work?).
RTM_DLY	4:0	RTM read delay. Valid values: 0 (0b00000) - 0ns 1 (0b00001) - 31.25ns 2 (0b00010) - 62.50ns 3 (0b00011) - 93.75ns 4 (0b00100) - 125ns 5 (0b00101) - 156.25ns 6 (0b00110) - 187.50ns 7 (0b00111) - 218.75ns 8 (0b01000) - 250ns 9 (0b01001) - 281.25ns 10 (0b01010) - 312.50ns 11 (0b01011) - 343.75ns 12 (0b01100) - 375ns 13 (0b01101) - 406.25ns 14 (0b01110) - 437.50ns 15 (0b01111) - 468.75ns 16 (0b10000) - 500ns 17 (0b10001) - 531.25ns 18 (0b10010) - 562.50ns 19 (0b10011) - 593.75ns 20 (0b10100) - 625ns 21 (0b10101) - 656.25ns 22 (0b10110) - 687.50ns 23 (0b10111) - 718.75ns 24 (0b11000) - 750ns 25 (0b11001) - 781.25ns 26 (0b11010) - 812.50ns 27 (0b11011) - 843.75ns 28 (0b11100) - 875ns 29 (0b11101) - 906.25ns 30 (0b11110) - 937.50ns 31 (0b11111) - 968.75ns

ADCCTRL3 - ADCCTRL28

ADC channel registers; see layout above.

ADCCTRL29 and ADCCTRL30

Unknown.