Mainline:Exynos 4/EMMC and SDHCI: Difference between revisions
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Converting from those structs: | Converting from those structs: | ||
== <code>exynos4_mshc_pdata</code> == | |||
'''Only if your device has <code>CONFIG_EXYNOS4_DEV_MSHC</code> enabled.''' | '''Only if your device has <code>CONFIG_EXYNOS4_DEV_MSHC</code> enabled.''' | ||
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* <code>int_power_gpio</code>: note down the GPIO and read on to “Regulator” section. | * <code>int_power_gpio</code>: note down the GPIO and read on to “Regulator” section. | ||
== <code>exynos_dwmci_pdata</code> == | |||
'''Only if your device has <code>CONFIG_EXYNOS4_DEV_DWMCI</code> enabled.''' | '''Only if your device has <code>CONFIG_EXYNOS4_DEV_DWMCI</code> enabled.''' | ||
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* Clocks are already set up | * Clocks are already set up | ||
== Pinctrl == | |||
Pinctrl may need to be set up according to width; see <code>exynos_dwmci_cfg_gpio</code> for DWMCI, <code>arch/arm/mach-exynos/setup-mshci-gpio.c</code> for MSHCI. There are premade pinctrl defaults <code>sdX_bus1</code>, <code>sdX_bus4</code> and <code>sdX_bus8</code> for width 1, 4 and 8 respectively (see midas DTSI for an example). | Pinctrl may need to be set up according to width; see <code>exynos_dwmci_cfg_gpio</code> for DWMCI, <code>arch/arm/mach-exynos/setup-mshci-gpio.c</code> for MSHCI. There are premade pinctrl defaults <code>sdX_bus1</code>, <code>sdX_bus4</code> and <code>sdX_bus8</code> for width 1, 4 and 8 respectively (see midas DTSI for an example). | ||
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Replace <code>X</code> with 0 or 4, depending on the contents of <code>exynos_dwmci_cfg_gpio</code> (or equivalent <code>.cfg_gpio</code> member of <code>exynos_dwmci_pdata</code> struct) function: if for width 8 it does <code>s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4));</code>, then 4, else 0. (The only difference between these two is the pin-function that’s set, see <code>exynos4x12-pinctrl.dtsi</code>.) In width 8, add both <code>bus4</code> and <code>bus8</code> (each has 4 pins, coming together to 8 pins total). | Replace <code>X</code> with 0 or 4, depending on the contents of <code>exynos_dwmci_cfg_gpio</code> (or equivalent <code>.cfg_gpio</code> member of <code>exynos_dwmci_pdata</code> struct) function: if for width 8 it does <code>s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4));</code>, then 4, else 0. (The only difference between these two is the pin-function that’s set, see <code>exynos4x12-pinctrl.dtsi</code>.) In width 8, add both <code>bus4</code> and <code>bus8</code> (each has 4 pins, coming together to 8 pins total). | ||
== Regulator == | |||
This depends on your device. Midas has a <code>VMEM_VDD_2.8V</code> regulator in its PMIC, your device might have something similar - check schematics. This will have to be enabled by the GPIO listed as <code>int_power_gpio</code> in your <code>exynos4_mshc_pdata</code> struct, probably <code>gpk0-2</code>. | This depends on your device. Midas has a <code>VMEM_VDD_2.8V</code> regulator in its PMIC, your device might have something similar - check schematics. This will have to be enabled by the GPIO listed as <code>int_power_gpio</code> in your <code>exynos4_mshc_pdata</code> struct, probably <code>gpk0-2</code>. | ||
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If you’re unsure, or if there’s no such regulator in your case, then you can create a <code>regulator-fixed</code> with a min/max voltage of 2.8V and enabled/disabled by said GPIO, and give <code>sdX_cd</code> pinctrl to it, or ignore it entirely and give the <code>sdX_cd</code> pinctrl to the <code>mshc_0</code> node. | If you’re unsure, or if there’s no such regulator in your case, then you can create a <code>regulator-fixed</code> with a min/max voltage of 2.8V and enabled/disabled by said GPIO, and give <code>sdX_cd</code> pinctrl to it, or ignore it entirely and give the <code>sdX_cd</code> pinctrl to the <code>mshc_0</code> node. | ||
== Timing values == | |||
Timing values are written to the <code>clksel</code> register on the MMC host, at offset <code>0x9c</code>. The timing values in mainline are the <code>sample</code> and <code>drive</code> values respectively. | Timing values are written to the <code>clksel</code> register on the MMC host, at offset <code>0x9c</code>. The timing values in mainline are the <code>sample</code> and <code>drive</code> values respectively. | ||