Mainline:Broadcom Kona/Timers: Difference between revisions
clarify STCM{0,3}_SYNC order |
fixup formatting on register names |
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| Line 99: | Line 99: | ||
!Description | !Description | ||
|- | |- | ||
| STCLO | | <code>STCLO</code> | ||
| 31:0 | | 31:0 | ||
| Lower 32 bits of the counter value. In 32-bit mode, this is the only register used for the counter value. | | Lower 32 bits of the counter value. In 32-bit mode, this is the only register used for the counter value. | ||
| Line 113: | Line 113: | ||
!Description | !Description | ||
|- | |- | ||
| STCHI | | <code>STCHI</code> | ||
| 31:0 | | 31:0 | ||
| Upper 32 bits of the counter value. Only used in 64-bit mode. | | Upper 32 bits of the counter value. Only used in 64-bit mode. | ||
| Line 127: | Line 127: | ||
!Description | !Description | ||
|- | |- | ||
| STCM{0,3} | | <code>STCM{0,3}</code> | ||
| 31:0 | | 31:0 | ||
| 32-bit time value for timer match. When the counter matches this value, the interrupt for the channel is raised and the bit corresponding to the triggered timer number is set in STCS_TIMER_MATCH. | | 32-bit time value for timer match. When the counter matches this value, the interrupt for the channel is raised and the bit corresponding to the triggered timer number is set in STCS_TIMER_MATCH. | ||