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Mainline:Broadcom Kona/Timers: Difference between revisions

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clarify STCM{0,3}_SYNC order
reorder STCS table
 
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== Starting the counter ==
== Starting the counter ==
To set the value and start counting:
* Set the value of <code>KONA_GPTIMER_STCM{n}</code> to the 32-bit value to match for (<code>{n}</code> is the number of the channel)
* Wait for the value to sync by watching the <code>STCM{n}_SYNC</code> value in <code>KONA_GPTIMER_STCS</code>
* In STCS, all in one write:
** Clear the timer match field (bits 3..0)
** Write the timer match bit for the selected channel (bits 3..0)
** Write the compare enable bit for the selected channel (bits 7..4)


== Local tick timer ==
== Local tick timer ==
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!Description
!Description
|-
|-
| <code>STCS_TIMER_MATCH</code>
| Reserved
| 3:0
| 31:16
| When the match registers STCM{0,3} match the counter, the interrupt for the matching channel is raised and a bit corresponding to the channel is set in this register.<br><br>- <code>0b0001</code> - channel 0 matches<br>- <code>0b0010</code> - channel 1 matches<br>- <code>0b0100</code> - channel 2 matches<br>- <code>0b1000</code> - channel 3 matches
| Reserved
|-
|-
| <code>STCS_COMPARE_ENABLE</code>
| <code>STCM{0,3}_SYNC</code>
| 7:4
| 15:12
| Enable compare (match) on the specified channel(s). When this bit is set, the value of the STCM{0,3} register will be used for a match.<br><br>- <code>0b0001</code> - enable compare for channel 0<br>- <code>0b0010</code> - enable compare for channel 1<br>- <code>0b0100</code> - enable compare for channel 2<br>- <code>0b1000</code> - enable compare for channel 3
| Sync bit for STCM{0,3} value being set (bit 12 is STCM0, bit 13 is STCM1, bit 14 is STCM2, bit 15 is STCM3).
|-
|-
| <code>STCS_COMPARE_ENABLE_SYNC</code>
| <code>STCS_COMPARE_ENABLE_SYNC</code>
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| Sync bit for COMPARE_ENABLE. Same layout as the above.
| Sync bit for COMPARE_ENABLE. Same layout as the above.
|-
|-
| <code>STCM{0,3}_SYNC</code>
| <code>STCS_COMPARE_ENABLE</code>
| 15:12
| 7:4
| Sync bit for STCM{0,3} value being set (bit 12 is STCM0, bit 13 is STCM1, bit 14 is STCM2, bit 15 is STCM3).
| Enable compare (match) on the specified channel(s). When this bit is set for a channel, the value of the STCM{0,3} register will be used for a match.<br><br>- <code>0b0001</code> - enable compare for channel 0<br>- <code>0b0010</code> - enable compare for channel 1<br>- <code>0b0100</code> - enable compare for channel 2<br>- <code>0b1000</code> - enable compare for channel 3
|-
|-
| Reserved
| <code>STCS_TIMER_MATCH</code>
| 31:16
| 3:0
| Reserved
| Represents the state of the timer interrupt for each channel; <code>0</code> means the interrupt is enabled, <code>1</code> means the interrupt is cleared.<br><br>To clean the interrupt, clean the entire field and set the bit corresponding to the channel to clear the interrupt for to <code>1</code>. {{Speculation|Leaving the other bits set to 0 while setting will keep the interrupt state intact (TODO - if not, then this means only one interrupt can be serviced at a time?)}}
|}
|}


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!Description
!Description
|-
|-
| STCLO
| <code>STCLO</code>
| 31:0
| 31:0
| Lower 32 bits of the counter value. In 32-bit mode, this is the only register used for the counter value.
| Lower 32 bits of the counter value. In 32-bit mode, this is the only register used for the counter value.
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!Description
!Description
|-
|-
| STCHI
| <code>STCHI</code>
| 31:0
| 31:0
| Upper 32 bits of the counter value. Only used in 64-bit mode.
| Upper 32 bits of the counter value. Only used in 64-bit mode.
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!Description
!Description
|-
|-
| STCM{0,3}
| <code>STCM{0,3}</code>
| 31:0
| 31:0
| 32-bit time value for timer match. When the counter matches this value, the interrupt for the channel is raised and the bit corresponding to the triggered timer number is set in STCS_TIMER_MATCH.
| 32-bit time value for timer match. When the lower bits of the counter match this value, the interrupt for the channel is raised and the bit corresponding to the triggered timer number is set in STCS_TIMER_MATCH.
|}
|}


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