Mainline:Exynos 4/EMMC and SDHCI - Revision history

Knuxify at 16:45, 21 January 2025

2025-01-21T16:45:40Z

← Older revision		Revision as of 18:45, 21 January 2025
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	Converting from those structs:		Converting from those structs:

	=== <code>exynos4_mshc_pdata</code> ===		== <code>exynos4_mshc_pdata</code> ==

	'''Only if your device has <code>CONFIG_EXYNOS4_DEV_MSHC</code> enabled.'''		'''Only if your device has <code>CONFIG_EXYNOS4_DEV_MSHC</code> enabled.'''
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	* <code>int_power_gpio</code>: note down the GPIO and read on to “Regulator” section.		* <code>int_power_gpio</code>: note down the GPIO and read on to “Regulator” section.

	=== <code>exynos_dwmci_pdata</code> ===		== <code>exynos_dwmci_pdata</code> ==

	'''Only if your device has <code>CONFIG_EXYNOS4_DEV_DWMCI</code> enabled.'''		'''Only if your device has <code>CONFIG_EXYNOS4_DEV_DWMCI</code> enabled.'''
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	* Clocks are already set up		* Clocks are already set up

	=== Pinctrl ===		== Pinctrl ==

	Pinctrl may need to be set up according to width; see <code>exynos_dwmci_cfg_gpio</code> for DWMCI, <code>arch/arm/mach-exynos/setup-mshci-gpio.c</code> for MSHCI. There are premade pinctrl defaults <code>sdX_bus1</code>, <code>sdX_bus4</code> and <code>sdX_bus8</code> for width 1, 4 and 8 respectively (see midas DTSI for an example).		Pinctrl may need to be set up according to width; see <code>exynos_dwmci_cfg_gpio</code> for DWMCI, <code>arch/arm/mach-exynos/setup-mshci-gpio.c</code> for MSHCI. There are premade pinctrl defaults <code>sdX_bus1</code>, <code>sdX_bus4</code> and <code>sdX_bus8</code> for width 1, 4 and 8 respectively (see midas DTSI for an example).
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	Replace <code>X</code> with 0 or 4, depending on the contents of <code>exynos_dwmci_cfg_gpio</code> (or equivalent <code>.cfg_gpio</code> member of <code>exynos_dwmci_pdata</code> struct) function: if for width 8 it does <code>s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4));</code>, then 4, else 0. (The only difference between these two is the pin-function that’s set, see <code>exynos4x12-pinctrl.dtsi</code>.) In width 8, add both <code>bus4</code> and <code>bus8</code> (each has 4 pins, coming together to 8 pins total).		Replace <code>X</code> with 0 or 4, depending on the contents of <code>exynos_dwmci_cfg_gpio</code> (or equivalent <code>.cfg_gpio</code> member of <code>exynos_dwmci_pdata</code> struct) function: if for width 8 it does <code>s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4));</code>, then 4, else 0. (The only difference between these two is the pin-function that’s set, see <code>exynos4x12-pinctrl.dtsi</code>.) In width 8, add both <code>bus4</code> and <code>bus8</code> (each has 4 pins, coming together to 8 pins total).

	=== Regulator ===		== Regulator ==

	This depends on your device. Midas has a <code>VMEM_VDD_2.8V</code> regulator in its PMIC, your device might have something similar - check schematics. This will have to be enabled by the GPIO listed as <code>int_power_gpio</code> in your <code>exynos4_mshc_pdata</code> struct, probably <code>gpk0-2</code>.		This depends on your device. Midas has a <code>VMEM_VDD_2.8V</code> regulator in its PMIC, your device might have something similar - check schematics. This will have to be enabled by the GPIO listed as <code>int_power_gpio</code> in your <code>exynos4_mshc_pdata</code> struct, probably <code>gpk0-2</code>.
Line 42:		Line 42:
	If you’re unsure, or if there’s no such regulator in your case, then you can create a <code>regulator-fixed</code> with a min/max voltage of 2.8V and enabled/disabled by said GPIO, and give <code>sdX_cd</code> pinctrl to it, or ignore it entirely and give the <code>sdX_cd</code> pinctrl to the <code>mshc_0</code> node.		If you’re unsure, or if there’s no such regulator in your case, then you can create a <code>regulator-fixed</code> with a min/max voltage of 2.8V and enabled/disabled by said GPIO, and give <code>sdX_cd</code> pinctrl to it, or ignore it entirely and give the <code>sdX_cd</code> pinctrl to the <code>mshc_0</code> node.

	=== Timing values ===		== Timing values ==

	Timing values are written to the <code>clksel</code> register on the MMC host, at offset <code>0x9c</code>. The timing values in mainline are the <code>sample</code> and <code>drive</code> values respectively.		Timing values are written to the <code>clksel</code> register on the MMC host, at offset <code>0x9c</code>. The timing values in mainline are the <code>sample</code> and <code>drive</code> values respectively.

Knuxify at 16:45, 21 January 2025

2025-01-21T16:45:12Z

← Older revision		Revision as of 18:45, 21 January 2025
Line 30:		Line 30:
	* Clocks are already set up		* Clocks are already set up

	~~<span id="pinctrl"></span>~~
	=== Pinctrl ===		=== Pinctrl ===

	Pinctrl may need to be set up according to width; see <code>exynos_dwmci_cfg_gpio</code> for DWMCI, <code>arch/arm/mach-exynos/setup-mshci-gpio.c</code> for MSHCI. There are premade pinctrl defaults <code>sdX_bus1</code>, <code>sdX_bus4</code> and <code>sdX_bus8</code> for width 1, 4 and 8 respectively (see midas DTSI for an example).		Pinctrl may need to be set up according to width; see <code>exynos_dwmci_cfg_gpio</code> for DWMCI, <code>arch/arm/mach-exynos/setup-mshci-gpio.c</code> for MSHCI. There are premade pinctrl defaults <code>sdX_bus1</code>, <code>sdX_bus4</code> and <code>sdX_bus8</code> for width 1, 4 and 8 respectively (see midas DTSI for an example).

	Replace <code>X</code> with 0 or 4, depending on the contents of <code>exynos_dwmci_cfg_gpio</code> (or equivalent <code>.cfg_gpio</code> member of <code>exynos_dwmci_pdata</code> struct) function: if for width 8 it does <code>s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4));</code>, then 4, else 0. (The only difference between these two is the pin-function that’s set, see <code>exynos4x12-pinctrl.dtsi</code>.) In width 8, add both <code>bus4</code> and <code>bus8</code> (each has 4 pins, coming together to 8 pins total). ~~###~~ Regulator		Replace <code>X</code> with 0 or 4, depending on the contents of <code>exynos_dwmci_cfg_gpio</code> (or equivalent <code>.cfg_gpio</code> member of <code>exynos_dwmci_pdata</code> struct) function: if for width 8 it does <code>s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4));</code>, then 4, else 0. (The only difference between these two is the pin-function that’s set, see <code>exynos4x12-pinctrl.dtsi</code>.) In width 8, add both <code>bus4</code> and <code>bus8</code> (each has 4 pins, coming together to 8 pins total).

			=== Regulator ===

	This depends on your device. Midas has a <code>VMEM_VDD_2.8V</code> regulator in its PMIC, your device might have something similar - check schematics. This will have to be enabled by the GPIO listed as <code>int_power_gpio</code> in your <code>exynos4_mshc_pdata</code> struct, probably <code>gpk0-2</code>.		This depends on your device. Midas has a <code>VMEM_VDD_2.8V</code> regulator in its PMIC, your device might have something similar - check schematics. This will have to be enabled by the GPIO listed as <code>int_power_gpio</code> in your <code>exynos4_mshc_pdata</code> struct, probably <code>gpk0-2</code>.
Line 41:		Line 42:
	If you’re unsure, or if there’s no such regulator in your case, then you can create a <code>regulator-fixed</code> with a min/max voltage of 2.8V and enabled/disabled by said GPIO, and give <code>sdX_cd</code> pinctrl to it, or ignore it entirely and give the <code>sdX_cd</code> pinctrl to the <code>mshc_0</code> node.		If you’re unsure, or if there’s no such regulator in your case, then you can create a <code>regulator-fixed</code> with a min/max voltage of 2.8V and enabled/disabled by said GPIO, and give <code>sdX_cd</code> pinctrl to it, or ignore it entirely and give the <code>sdX_cd</code> pinctrl to the <code>mshc_0</code> node.

	~~<span id="timing-values"></span>~~
	=== Timing values ===		=== Timing values ===

Knuxify: Created page with "This page contains notes regarding porting downstream kernel SDHCI/EMMC data to mainline. Main EMMC node is `mshc_0`; the data for it is stored in structs `exynos_dwmci_pdata` and `exynos4_mshc_pdata`. See `Documentation/devicetree/bindings/mmc/mmc-controller.yaml`. Converting from those structs: === `exynos4_mshc_pdata` === '''Only if your device has `CONFIG_EXYNOS4_DEV_MSHC` enabled.''' * `cd_..."`


2025-01-21T16:44:16Z
Created page with "This page contains notes regarding porting downstream kernel SDHCI/EMMC data to mainline.  Main EMMC node is <code>mshc_0</code>; the data for it is stored in structs <code>exynos_dwmci_pdata</code> and <code>exynos4_mshc_pdata</code>.  See <code>Documentation/devicetree/bindings/mmc/mmc-controller.yaml</code>.  Converting from those structs:  === <code>exynos4_mshc_pdata</code> ===  '''Only if your device has <code>CONFIG_EXYNOS4_DEV_MSHC</code> enabled.'''  * <code>cd_..."
New page
This page contains notes regarding porting downstream kernel SDHCI/EMMC data to mainline.



Main EMMC node is <code>mshc_0</code>; the data for it is stored in structs <code>exynos_dwmci_pdata</code> and <code>exynos4_mshc_pdata</code>.



See <code>Documentation/devicetree/bindings/mmc/mmc-controller.yaml</code>.



Converting from those structs:



=== <code>exynos4_mshc_pdata</code> ===



'''Only if your device has <code>CONFIG_EXYNOS4_DEV_MSHC</code> enabled.'''



* <code>cd_type</code>: probably S3C_MSHCI_CD_PERMANENT, in which case, <code>non-removable;</code>

* <code>caps</code>: see mmc-controller.yaml, they’re pretty much the same

* <code>int_power_gpio</code>: note down the GPIO and read on to “Regulator” section.



=== <code>exynos_dwmci_pdata</code> ===



'''Only if your device has <code>CONFIG_EXYNOS4_DEV_DWMCI</code> enabled.'''



* <code>quirks</code>:

** <code>DW_MCI_QUIRK_BROKEN_CARD_DETECTION</code> -&gt; <code>broken-cd;</code>

** <code>DW_MCI_QUIRK_HIGHSPEED</code> -&gt; <code>cap-mmc-highspeed</code>

* <code>bus_hz</code> -&gt; <code>clock-frequency: &lt;FIXME&gt;;</code>

* <code>caps</code>: see mmc-controller.yaml, they’re pretty much the same

** <code>MMC_CAP_CMD23</code> is enabled by default, no need to add it

** <code>MMC_CAP_8_BIT_DATA</code> is <code>bus-width = &lt;8&gt;;</code>

* <code>detect_delay_ms</code> -&gt; <code>card-detect-delay = &lt;FIXME&gt;;</code>

* <code>fifo-depth</code> -&gt; <code>fifo-depth = &lt;0xFIXME&gt;;</code> (note: 0x80 is default, so skip this if it’s 0x80 on your device)

* Clocks are already set up



<span id="pinctrl"></span>

=== Pinctrl ===



Pinctrl may need to be set up according to width; see <code>exynos_dwmci_cfg_gpio</code> for DWMCI, <code>arch/arm/mach-exynos/setup-mshci-gpio.c</code> for MSHCI. There are premade pinctrl defaults <code>sdX_bus1</code>, <code>sdX_bus4</code> and <code>sdX_bus8</code> for width 1, 4 and 8 respectively (see midas DTSI for an example).



Replace <code>X</code> with 0 or 4, depending on the contents of <code>exynos_dwmci_cfg_gpio</code> (or equivalent <code>.cfg_gpio</code> member of <code>exynos_dwmci_pdata</code> struct) function: if for width 8 it does <code>s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4));</code>, then 4, else 0. (The only difference between these two is the pin-function that’s set, see <code>exynos4x12-pinctrl.dtsi</code>.) In width 8, add both <code>bus4</code> and <code>bus8</code> (each has 4 pins, coming together to 8 pins total). ### Regulator



This depends on your device. Midas has a <code>VMEM_VDD_2.8V</code> regulator in its PMIC, your device might have something similar - check schematics. This will have to be enabled by the GPIO listed as <code>int_power_gpio</code> in your <code>exynos4_mshc_pdata</code> struct, probably <code>gpk0-2</code>.



If you’re unsure, or if there’s no such regulator in your case, then you can create a <code>regulator-fixed</code> with a min/max voltage of 2.8V and enabled/disabled by said GPIO, and give <code>sdX_cd</code> pinctrl to it, or ignore it entirely and give the <code>sdX_cd</code> pinctrl to the <code>mshc_0</code> node.



<span id="timing-values"></span>

=== Timing values ===



Timing values are written to the <code>clksel</code> register on the MMC host, at offset <code>0x9c</code>. The timing values in mainline are the <code>sample</code> and <code>drive</code> values respectively.



For tab3 downstream, they seem to be set in <code>arch/arm/mach-exynos/dev-dwmci.c</code>, and are the same for all devices.



For MSHCI, the values are hardcoded in <code>drivers/mmc/host/mshci.c</code> line 1252 and onwards.



DDR value is for DDR_50 mode, SDR is for non-DDR_50. Both of the aforementioned files have ifs for checking this.



To decode a CLKSEL value, run this python script



<syntaxhighlight lang="python3">value = 0x00010001  # CHANGE THIS



print("Sample:", (clksel_val >> 0) & 7)

print("Drive:", (clksel_val >> 8) & 7)

print("Divider:", (clksel_val >> 16) & 7)</syntaxhighlight>

However, the sample value seems to be tuned at runtime using the built-in tune function. Unclear how this works yet, TODO.



Divider is <code>samsung,dw-mshc-ciu-div</code>, but is ignored for Exynos4412 anyways, TODO? See <code>drivers/mmc/host/dw_mmc-exynos.c</code> in mainline. Sample and drive are passed to the timing values in that order.



…Our best bet is probably to get those values from a running device, somehow…