Mainline:Broadcom Kona/Timers - Revision history

Knuxify: reorder STCS table

2025-03-13T19:43:09Z

reorder STCS table

← Older revision		Revision as of 21:43, 13 March 2025
Line 78:		Line 78:
	!Description		!Description
	\|-		\|-
	\| ~~<code>STCS_TIMER_MATCH</code>~~		\| Reserved
	\| 3:0		\| 31:16
	\| Represents the state of the timer interrupt for each channel; <code>0</code> means the interrupt is enabled, <code>1</code> means the interrupt is cleared.<br><br>To clean the interrupt, clean the entire field and set the bit corresponding to the channel to clear the interrupt for to <code>1</code>. {{Speculation\|Leaving the other bits set to 0 while setting will keep the interrupt state intact (TODO - if not, then this means only one interrupt can be serviced at a time?)}}		\| Reserved
	\|-		\|-
	\| <code>~~STCS_COMPARE_ENABLE~~</code>		\| <code>STCM{0,3}_SYNC</code>
	\| 7:4		\| 15:12
	\| ~~Enable compare (match) on the specified channel(s). When this~~ bit ~~is set~~ for ~~a channel, the value of the~~ STCM{0,3} ~~register will be used for a match~~.<br><br>- <code>0b0001</code> - enable compare for channel 0<br>- <code>0b0010</code> - enable compare for channel 1<br>- <code>0b0100</code> - enable compare for channel 2<br>- <code>0b1000</code> - enable compare for channel 3		\| Sync bit for STCM{0,3} value being set (bit 12 is STCM0, bit 13 is STCM1, bit 14 is STCM2, bit 15 is STCM3).
	\|-		\|-
	\| <code>STCS_COMPARE_ENABLE_SYNC</code>		\| <code>STCS_COMPARE_ENABLE_SYNC</code>
Line 90:		Line 90:
	\| Sync bit for COMPARE_ENABLE. Same layout as the above.		\| Sync bit for COMPARE_ENABLE. Same layout as the above.
	\|-		\|-
	\| <code>~~STCM{0,3}_SYNC~~</code>		\| <code>STCS_COMPARE_ENABLE</code>
	\| 15:12		\| 7:4
	\| ~~Sync~~ bit for STCM{0,3} ~~value being set (bit 12 is STCM0, bit 13 is STCM1, bit 14 is STCM2, bit 15 is STCM3)~~.		\| Enable compare (match) on the specified channel(s). When this bit is set for a channel, the value of the STCM{0,3} register will be used for a match.<br><br>- <code>0b0001</code> - enable compare for channel 0<br>- <code>0b0010</code> - enable compare for channel 1<br>- <code>0b0100</code> - enable compare for channel 2<br>- <code>0b1000</code> - enable compare for channel 3
	\|-		\|-
	\| ~~Reserved~~		\| <code>STCS_TIMER_MATCH</code>
	\| 31:16		\| 3:0
	\| ~~Reserved~~		\| Represents the state of the timer interrupt for each channel; <code>0</code> means the interrupt is enabled, <code>1</code> means the interrupt is cleared.<br><br>To clean the interrupt, clean the entire field and set the bit corresponding to the channel to clear the interrupt for to <code>1</code>. {{Speculation\|Leaving the other bits set to 0 while setting will keep the interrupt state intact (TODO - if not, then this means only one interrupt can be serviced at a time?)}}
	\|}		\|}

Knuxify: /* KONA_GPTIMER_STCM{0,3} (0x0c, 0x10, 0x14, 0x18) */

2025-03-13T19:39:28Z

KONA_GPTIMER_STCM{0,3} (0x0c, 0x10, 0x14, 0x18)

← Older revision		Revision as of 21:39, 13 March 2025
Line 138:		Line 138:
	\| <code>STCM{0,3}</code>		\| <code>STCM{0,3}</code>
	\| 31:0		\| 31:0
	\| 32-bit time value for timer match. When the counter ~~matches~~ this value, the interrupt for the channel is raised and the bit corresponding to the triggered timer number is set in STCS_TIMER_MATCH.		\| 32-bit time value for timer match. When the lower bits of the counter match this value, the interrupt for the channel is raised and the bit corresponding to the triggered timer number is set in STCS_TIMER_MATCH.
	\|}		\|}

Knuxify at 20:41, 23 January 2025

2025-01-23T20:41:06Z

← Older revision		Revision as of 22:41, 23 January 2025
Line 62:		Line 62:
	** Write the timer match bit for the selected channel (bits 3..0)		** Write the timer match bit for the selected channel (bits 3..0)
	** Write the compare enable bit for the selected channel (bits 7..4)		** Write the compare enable bit for the selected channel (bits 7..4)


	== Local tick timer ==		== Local tick timer ==
Line 81:		Line 80:
	\| <code>STCS_TIMER_MATCH</code>		\| <code>STCS_TIMER_MATCH</code>
	\| 3:0		\| 3:0
	\| Represents the state of the timer interrupt for each channel; <code>0</code> means the interrupt is enabled, <code>1</code> means the interrupt is cleared.<br><br>To clean the interrupt, clean the entire field and set the bit corresponding to the channel to clear the interrupt for to <code>1</code>.		\| Represents the state of the timer interrupt for each channel; <code>0</code> means the interrupt is enabled, <code>1</code> means the interrupt is cleared.<br><br>To clean the interrupt, clean the entire field and set the bit corresponding to the channel to clear the interrupt for to <code>1</code>. {{Speculation\|Leaving the other bits set to 0 while setting will keep the interrupt state intact (TODO - if not, then this means only one interrupt can be serviced at a time?)}}
	\|-		\|-
	\| <code>STCS_COMPARE_ENABLE</code>		\| <code>STCS_COMPARE_ENABLE</code>

Knuxify at 20:32, 23 January 2025

2025-01-23T20:32:04Z

← Older revision		Revision as of 22:32, 23 January 2025
Line 53:		Line 53:

	== Starting the counter ==		== Starting the counter ==

			To set the value and start counting:

			* Set the value of <code>KONA_GPTIMER_STCM{n}</code> to the 32-bit value to match for (<code>{n}</code> is the number of the channel)
			* Wait for the value to sync by watching the <code>STCM{n}_SYNC</code> value in <code>KONA_GPTIMER_STCS</code>
			* In STCS, all in one write:
			** Clear the timer match field (bits 3..0)
			** Write the timer match bit for the selected channel (bits 3..0)
			** Write the compare enable bit for the selected channel (bits 7..4)


	== Local tick timer ==		== Local tick timer ==
Line 71:		Line 81:
	\| <code>STCS_TIMER_MATCH</code>		\| <code>STCS_TIMER_MATCH</code>
	\| 3:0		\| 3:0
	\| ~~Timer match interrupt. When~~ the ~~match registers STCM{0,3} match the counter,~~ the interrupt for ~~the matching~~ channel ~~is raised and the corresponding bit (0 for channel 0, 1 for channel 1, etc.) is set to~~ <code>0</code>~~. Setting~~ the ~~bit to~~ <code>1</code> ~~clears~~ the interrupt~~; setting~~ the bit to <code>0</code> ~~keeps it as-is~~.~~<br><br>(TODO: does this mean that 1 is "interrupt off" and 0 is "interrupt on"?)~~		\| Represents the state of the timer interrupt for each channel; <code>0</code> means the interrupt is enabled, <code>1</code> means the interrupt is cleared.<br><br>To clean the interrupt, clean the entire field and set the bit corresponding to the channel to clear the interrupt for to <code>1</code>.
	\|-		\|-
	\| <code>STCS_COMPARE_ENABLE</code>		\| <code>STCS_COMPARE_ENABLE</code>
	\| 7:4		\| 7:4
	\| Enable compare (match) on the specified channel(s). When this bit is set, the value of the STCM{0,3} register will be used for a match.<br><br>- <code>0b0001</code> - enable compare for channel 0<br>- <code>0b0010</code> - enable compare for channel 1<br>- <code>0b0100</code> - enable compare for channel 2<br>- <code>0b1000</code> - enable compare for channel 3		\| Enable compare (match) on the specified channel(s). When this bit is set for a channel, the value of the STCM{0,3} register will be used for a match.<br><br>- <code>0b0001</code> - enable compare for channel 0<br>- <code>0b0010</code> - enable compare for channel 1<br>- <code>0b0100</code> - enable compare for channel 2<br>- <code>0b1000</code> - enable compare for channel 3
	\|-		\|-
	\| <code>STCS_COMPARE_ENABLE_SYNC</code>		\| <code>STCS_COMPARE_ENABLE_SYNC</code>

Knuxify: fix timer_match desc - downstream code and decompiled loader both clear all 4 bits of timer_match before writing 1 to disarm the one interrupt they want to disarm

2025-01-23T20:08:15Z

fix timer_match desc - downstream code and decompiled loader both clear all 4 bits of timer_match before writing 1 to disarm the one interrupt they want to disarm

← Older revision		Revision as of 22:08, 23 January 2025
Line 71:		Line 71:
	\| <code>STCS_TIMER_MATCH</code>		\| <code>STCS_TIMER_MATCH</code>
	\| 3:0		\| 3:0
	\| When the match registers STCM{0,3} match the counter, the interrupt for the matching channel is raised and a bit ~~corresponding to the~~ channel is set ~~in this register.<br><br>-~~ <code>~~0b0001~~</code> ~~- channel 0 matches<br>-~~ <code>~~0b0010~~</code> ~~- channel 1 matches<br>-~~ <code>~~0b0100~~</code> - ~~channel 2 matches~~<br>- <~~code~~>~~0b1000</code> - channel 3 matches~~		\| Timer match interrupt. When the match registers STCM{0,3} match the counter, the interrupt for the matching channel is raised and the corresponding bit (0 for channel 0, 1 for channel 1, etc.) is set to <code>0</code>. Setting the bit to <code>1</code> clears the interrupt; setting the bit to <code>0</code> keeps it as-is.<br><br>(TODO: does this mean that 1 is "interrupt off" and 0 is "interrupt on"?)
	\|-		\|-
	\| <code>STCS_COMPARE_ENABLE</code>		\| <code>STCS_COMPARE_ENABLE</code>

Knuxify: fixup formatting on register names

2025-01-21T08:21:40Z

fixup formatting on register names

← Older revision		Revision as of 10:21, 21 January 2025
Line 99:		Line 99:
	!Description		!Description
	\|-		\|-
	\| STCLO		\| <code>STCLO</code>
	\| 31:0		\| 31:0
	\| Lower 32 bits of the counter value. In 32-bit mode, this is the only register used for the counter value.		\| Lower 32 bits of the counter value. In 32-bit mode, this is the only register used for the counter value.
Line 113:		Line 113:
	!Description		!Description
	\|-		\|-
	\| STCHI		\| <code>STCHI</code>
	\| 31:0		\| 31:0
	\| Upper 32 bits of the counter value. Only used in 64-bit mode.		\| Upper 32 bits of the counter value. Only used in 64-bit mode.
Line 127:		Line 127:
	!Description		!Description
	\|-		\|-
	\| STCM{0,3}		\| <code>STCM{0,3}</code>
	\| 31:0		\| 31:0
	\| 32-bit time value for timer match. When the counter matches this value, the interrupt for the channel is raised and the bit corresponding to the triggered timer number is set in STCS_TIMER_MATCH.		\| 32-bit time value for timer match. When the counter matches this value, the interrupt for the channel is raised and the bit corresponding to the triggered timer number is set in STCS_TIMER_MATCH.

Knuxify: clarify STCM{0,3}_SYNC order

2025-01-21T07:53:53Z

clarify STCM{0,3}_SYNC order

← Older revision		Revision as of 09:53, 21 January 2025
Line 83:		Line 83:
	\| <code>STCM{0,3}_SYNC</code>		\| <code>STCM{0,3}_SYNC</code>
	\| 15:12		\| 15:12
	\| Sync bit for STCM{0,3} value being set.		\| Sync bit for STCM{0,3} value being set (bit 12 is STCM0, bit 13 is STCM1, bit 14 is STCM2, bit 15 is STCM3).
	\|-		\|-
	\| Reserved		\| Reserved

Knuxify: /* Timer initialization in downstream */

2025-01-21T07:51:46Z

Timer initialization in downstream

← Older revision		Revision as of 09:51, 21 January 2025
Line 138:		Line 138:
	** Calls <code>timers_init</code>, which 1. sets up clock rates, 2. calls <code>kona_timer_config</code> on the GP timer from the struct;		** Calls <code>timers_init</code>, which 1. sets up clock rates, 2. calls <code>kona_timer_config</code> on the GP timer from the struct;
	*** Sets a callback function, <code>gptimer_interrupt_cb</code> to call on timer interrupt.		*** Sets a callback function, <code>gptimer_interrupt_cb</code> to call on timer interrupt.

			Downstream driver: https://github.com/knuxdroid/android_kernel_samsung_baffinlite/blob/cm-12.1/arch/arm/plat-kona/kona_timer.c

Knuxify: /* Timer regs */

2025-01-20T16:54:40Z

Timer regs

← Older revision		Revision as of 18:54, 20 January 2025
Line 65:		Line 65:

	{\|class="wikitable"		{\|class="wikitable"
	!~~width="7%"\|~~ Name		!Name
	!~~width="1%"\|~~ Bit		!Bit
	!~~width="90%"\|~~ Description		!Description
	\|-		\|-
	\| <code>STCS_TIMER_MATCH</code>		\| <code>STCS_TIMER_MATCH</code>
Line 95:		Line 95:

	{\|class="wikitable"		{\|class="wikitable"
	!~~width="5%"\|~~ Name		!Name
	!~~width="4%"\|~~ Bit		!Bit
	!~~width="90%"\|~~ Description		!Description
	\|-		\|-
	\| STCLO		\| STCLO
Line 109:		Line 109:

	{\|class="wikitable"		{\|class="wikitable"
	! Name		!Name
	! Bit		!Bit
	! Description		!Description
	\|-		\|-
	\| STCHI		\| STCHI
Line 123:		Line 123:

	{\|class="wikitable"		{\|class="wikitable"
	!~~width="4%"\|~~ Name		!Name
	!~~width="2%"\|~~ Bit		!Bit
	!~~width="92%"\|~~ Description		!Description
	\|-		\|-
	\| STCM{0,3}		\| STCM{0,3}

Knuxify: Created page with "The Kona platform has three timers: * HUB/AON * Slave/Peripheral * (BCM23550 only) Core The driver for the timers is split up into three files: * `arch/arm/plat-kona/kona_timer.c` * `arch/arm/plat-kona/timer.c` * `arch/arm/plat-kona/localtimer.c` - setup for the local tick timer (local, I assume, means "CPU-local" - meaning each channel belongs to a different CPU core) All timers use the same driver. == Timer operation == Each timer..."

2025-01-20T15:50:04Z

Created page with "The Kona platform has three timers: * HUB/AON * Slave/Peripheral * (BCM23550 only) Core The driver for the timers is split up into three files: * <code>arch/arm/plat-kona/kona_timer.c</code> * <code>arch/arm/plat-kona/timer.c</code> * <code>arch/arm/plat-kona/localtimer.c</code> - setup for the local tick timer (local, I assume, means "CPU-local" - meaning each channel belongs to a different CPU core) All timers use the same driver. == Timer operation == Each timer..."

New page

The Kona platform has three timers:

* HUB/AON
* Slave/Peripheral
* (BCM23550 only) Core

The driver for the timers is split up into three files:

* <code>arch/arm/plat-kona/kona_timer.c</code>
* <code>arch/arm/plat-kona/timer.c</code>
* <code>arch/arm/plat-kona/localtimer.c</code> - setup for the local tick timer (local, I assume, means "CPU-local" - meaning each channel belongs to a different CPU core)

All timers use the same driver.

== Timer operation ==

Each timer device manages '''4 channels'''. Each channel has its own separate IRQ.

The timer operates in '''oneshot mode''', meaning that it can be programmed to generate a clock event once (as opposed to PERIODIC mode which generates periodical events). See https://elixir.bootlin.com/linux/v6.10.6/source/include/linux/clockchips.h#L22. Downstream has some code to emulate periodic timers.

Due to hardware limitations, there is a delay of 5 clock cycles when writing values to the timers. Downstream claims that this is only true for HUB timer, but applies the mitigation to all timers. (https://github.com/knuxdroid/android_kernel_samsung_baffinlite/blob/cm-12.1/arch/arm/plat-kona/localtimer.c#L176-L179)

== Timer rate ==

The Hub/AON timer uses the <code>TIMERS</code> clock, which can be set to either 32KHz or 1MHz. (Downstream also claims it can use 19.5MHz, but the clock doesn't have the setting for it; if it did, it would have the selector value of 2. I assume either kona_timer.c or clock driver is mistaken.)

== Getting the counter value ==

'''In 64-bit mode:''' Read the value of <code>KONA_GPTIMER_STCLO_OFFSET</code> (<code>0x04</code>) to get the low 32 bits, and <code>KONA_GPTIMER_STCHI_OFFSET</code> (<code>0x08</code>) to get the high 32 bits, then combine to get the full value.

'''In 32-bit mode:''' Read the value of <code>KONA_GPTIMER_STCLO_OFFSET</code> (<code>0x04</code>).

It's worth noting that despite the timer being capable of counting to 64 bits, the downstream driver overrides this for the hub timer. The reasoning is that the match values used for each channel are 32-bit. (Slave/Peripheral does not use channels? TODO) (https://github.com/knuxdroid/android_kernel_samsung_baffinlite/blob/cm-12.1/arch/arm/plat-kona/timer.c#L137-L142)

Switching to 32-bit mode is done by writing to the CHIPREG register. For Rhea, Hawaii and Java, this is done as such: (https://github.com/knuxdroid/android_kernel_samsung_baffinlite/blob/cm-12.1/arch/arm/plat-kona/kona_timer.c#L322-L326)

<syntaxhighlight lang="c">
/* Configure KONA Timer count in 32 bit mode */
writel(0x0, KONA_CHIPREG_VA + CHIPREG_HUB_TIMER_WIDTH_OFFSET);
</syntaxhighlight>

For Capri, this is done as such: (https://github.com/ghsr/android_kernel_samsung_i9152/blob/android-7.1/arch/arm/plat-kona/kona_timer.c#L268-L271)

<syntaxhighlight lang="c">
/* Use 32bit mode timer */
reg = readl(KONA_CHIPREG_VA + CHIPREG_ARM_PERI_CONTROL_OFFSET);
reg &= ~(CHIPREG_ARM_PERI_CONTROL_SLV_TIMER_64BITMODE_MASK |
CHIPREG_ARM_PERI_CONTROL_HUB_TIMER_64BITMODE_MASK);
writel(reg, KONA_CHIPREG_VA + CHIPREG_ARM_PERI_CONTROL_OFFSET);
</syntaxhighlight>

Note that on Capri, it seems to set both the Hub and the Slave/Peripheral timer to 32-bit mode, whereas on Rhea/Hawaii/Java only Hub timer is configured (Slave/Peripheral timer has a separate width offset at <code>CHIPREG_SLAVE_TIMER_WIDTH_OFFSET</code>).

== Starting the counter ==

== Local tick timer ==

The '''local tick timer''' refers to the timer the channels of which are used as CPU-local timers. In downstream, it's set up in <code>arch/arm/plat-kona/localtimer.c</code>.

== Timer regs ==

=== KONA_GPTIMER_STCS (<code>0x00</code>) ===

Settings register. Contains controls for the timer's state.

{|class="wikitable"
!width="7%"| Name
!width="1%"| Bit
!width="90%"| Description
|-
| <code>STCS_TIMER_MATCH</code>
| 3:0
| When the match registers STCM{0,3} match the counter, the interrupt for the matching channel is raised and a bit corresponding to the channel is set in this register. - <code>0b0001</code> - channel 0 matches - <code>0b0010</code> - channel 1 matches - <code>0b0100</code> - channel 2 matches - <code>0b1000</code> - channel 3 matches
|-
| <code>STCS_COMPARE_ENABLE</code>
| 7:4
| Enable compare (match) on the specified channel(s). When this bit is set, the value of the STCM{0,3} register will be used for a match. - <code>0b0001</code> - enable compare for channel 0 - <code>0b0010</code> - enable compare for channel 1 - <code>0b0100</code> - enable compare for channel 2 - <code>0b1000</code> - enable compare for channel 3
|-
| <code>STCS_COMPARE_ENABLE_SYNC</code>
| 11:8
| Sync bit for COMPARE_ENABLE. Same layout as the above.
|-
| <code>STCM{0,3}_SYNC</code>
| 15:12
| Sync bit for STCM{0,3} value being set.
|-
| Reserved
| 31:16
| Reserved
|}

=== KONA_GPTIMER_STCLO (<code>0x04</code>) ===

Contains the lower 32 bits of the counter value.

{|class="wikitable"
!width="5%"| Name
!width="4%"| Bit
!width="90%"| Description
|-
| STCLO
| 31:0
| Lower 32 bits of the counter value. In 32-bit mode, this is the only register used for the counter value.
|}

=== KONA_GPTIMER_STCHI (<code>0x08</code>) ===

Contains the upper 32 bits of the counter value.

{|class="wikitable"
! Name
! Bit
! Description
|-
| STCHI
| 31:0
| Upper 32 bits of the counter value. Only used in 64-bit mode.
|}

=== KONA_GPTIMER_STCM{0,3} (<code>0x0c</code>, <code>0x10</code>, <code>0x14</code>, <code>0x18</code>) ===

Match registers for channels 0-3.

{|class="wikitable"
!width="4%"| Name
!width="2%"| Bit
!width="92%"| Description
|-
| STCM{0,3}
| 31:0
| 32-bit time value for timer match. When the counter matches this value, the interrupt for the channel is raised and the bit corresponding to the triggered timer number is set in STCS_TIMER_MATCH.
|}

== Timer initialization in downstream ==

* Starts in <code>hawaii_timer_init</code> in hawaii.c (https://github.com/knuxdroid/android_kernel_samsung_baffinlite/blob/cm-12.1/arch/arm/mach-hawaii/hawaii.c#L176-L208)
* This sets up a GP timer setup struct and calls <code>gp_timer_init</code>, which is placed in <code>arch/arm/plat-kona/timer.c</code> (https://github.com/knuxdroid/android_kernel_samsung_baffinlite/blob/cm-12.1/arch/arm/plat-kona/timer.c#L262C1-L305C2)
** Calls <code>timers_init</code>, which 1. sets up clock rates, 2. calls <code>kona_timer_config</code> on the GP timer from the struct;
*** Sets a callback function, <code>gptimer_interrupt_cb</code> to call on timer interrupt.